library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(	clk,rst:in std_logic;
		ge:buffer integer;
		shi:buffer integer);
end entity counter;

architecture funs of counter is
	
begin
process(clk,rst)
begin
	if rst='1' then
		ge<=0;shi<=0;
	elsif clk'event and clk='1' then
		if ge=9 then
			shi<=shi+1;
			ge<=0;
			if shi=10 then
			shi<=0;
			end if;
		else ge<=ge+1; 
		end if;
		
	end if;	
end process;
end architecture funs; 
	
	
	
	
	
	
		